Memories typically include a plurality of memory cells, which may be arranged in an array of intersecting rows and columns. Read and write operations, to respectively store and retrieve memory contents, may involve multiple steps and accessing multiple memory cells at approximately the same time. One or more clock signals can serve to synchronize activities in a memory. Such clock signals can be distributed throughout the memory through its clock distribution network. Various components of a clock path, for example clock drivers and delay cells of a delay line, can be sensitive to variations in supply voltage and/or current used to power the memory. Clock path constituents can differ in their sensitivity to supply variations.
Memory devices are commonly powered by a variety of means. In some cases, the circuits are powered solely from an external source coupled to a power supply terminal. Memory device suppliers can specify minimum and maximum supply voltage and/or current (i.e., operating parameters) for proper operation of the memory device. Even within specified operating parameters, components of a clock path may exhibit different levels of sensitivity to supply variations sufficient to cause timing variations of the clock signal and outputs.
Circuits in a clock path that include delay circuits, for example, delay-lock loops, duty cycle correction circuits, clock generators, and other circuits, may introduce significant timing variation resulting from power supply sensitivity because each delay circuit may add a timing variation. Moreover, the delay circuits may have different responses to power supply variation, resulting in differing degrees of timing variations over a range of power supply variation. Whereas the timing variation introduced by each delay circuit may not be significant, the sum of the timing variations contributed by all of the delay circuits and the differences in power supply sensitivities may be enough to cause problems in operation.